1. Field of Applicable Technology
The present invention relates to a circuit of a sense amplifier for amplifying a signal voltage produced by reading the contents of a memory cell of a semiconductor memory. In particular, the invention relates to an improved sense amplifier circuit whereby a high speed of read-out operation can be achieved while limiting the maximum bit line voltage such as to ensure reliability of a memory cell oxide film.
2. Prior Art Technology
FIG. 1 is a circuit diagram of an example of a prior art sense amplifier circuit, while FIG. 2 shows waveforms appearing in the circuit of FIG. 2. This will be referred to as a P-type sense amplifier circuit, since the circuit is based on P-channel MOS FETs (field effect transistors). Numeral 2 denotes a pair of bit lines of a semiconductor memory, with each of the bit lines being coupled to a row of memory cells 8. A pair of P-channel MOS transistor have the gate and drain electrodes thereof mutually cross-coupled to form a flip-flop 1, with the drain electrodes being respectively connected to the bit line pair 2 as shown. The source electrodes of these transistors are mutually connected, with that junction being referred to in the following as a common node. The common node of the P-type flip-flop 1 is connected to the drain electrode of a P-channel MOS transistor 3 which functions as a switching element, and whose source electrode is coupled to receive an internal supply voltage V.sub.cc '. An external supply voltage V.sub.cc, e.g. provided from a main power supply unit and having a value of +5.0 V for example, is supplied to the internal voltage generating circuit 4. The internal voltage generating circuit 4 serves to generate the internal supply voltage V.sub.cc ', which has a fixed value that can be for example in the range +3 to +4 V, and is supplied via a line 6 to the switching transistor 3.
The internal voltage generating circuit 4 is used to produce an internal supply voltage which is of smaller magnitude than the system power supply voltage in order to limit the voltage level that is supplied by the switching transistor 3 to the common node of the P-type flip-flop 1. This is done in order to ensure the reliability of the oxide film of the memory cells 8 of the semiconductor memory.
An example of a circuit of the internal voltage generating circuit 4 is shown within the broken-line rectangle in FIG. 1.
The operation of this circuit will be described referring to the waveform diagrams of FIG. 2, in which waveform (A) is that of a word line 7 of the semiconductor memory, (B) is that of a gate control signal that is applied to the gate electrode of the switching transistor 3, and (C) is the waveform of a differential voltage that appears between the bit line pair 2. Firstly, when a memory cell 8 of one of the bit lines 2 is selected, by raising the word line potential from a low to a high level as shown, then after a short interval has elapsed, the gate potential of the switching transistor 3 is set from a high to a low level, to thereby turn the switching transistor 3 to the conducting (ON) state. The P-type flip-flop 1 is thereby activated, and if an output voltage is generated from the selected memory cell (e.g. due to a "1" state bit being stored therein) then a differential voltage .DELTA.V will be produced between the two bit lines 2. That is, the respective voltages of the two bit lines 2, designated as V.sub.a, V.sub. b in waveform (C), will begin to mutually differ. The P-type flip-flop 1 is thereby triggered, causing the differential voltage to be amplified, as shown in FIG. 2(C).
FIG. 3 shows an example of a prior art N-type sense amplifier. This is basically similar to the P-type sense amplifier described above, but employs N-channel MOS transistor. An N-channel MOS transistor 30 functions as a switching element, for transferring a supply voltage V.sub.ss (which in this case is ground potential) to the common node of a N-type flip-flop 10. An internal voltage generating circuit 40 produces a back-bias voltage V.sub.bb ' which is used to set the substrate potential of each of the N-channel MOS transistor, i.e. to apply a bias voltage which is negative with respect to V.sub.ss.
A typical circuit configuration for the internal voltage generating circuit 40 is shown within the broken-line rectangle.
The operation of this circuit is illustrated by the waveforms (A), (B) and (C) of FIG. 4. In this case, shortly after a memory cell has been selected, by the corresponding word line going from the low to the high level, the switching control signal (i.e. gate control voltage of the switching transistor 30) is set from the low to the high level, to thereby set the switching transistor 30 in the conducting state. The N-type flip-flop 10 is thereby activated, and if the selected memory cell generates an output voltage, the resultant voltage difference between the corresponding bit line pair 2 will trigger the N-type flip-flop 10. Thus, the differential voltage V is amplified and thereby increases as shown in waveform (C), thereby triggering the N-type flip-flop 10, and so amplifying the differential voltage between the bit line pair 2.
With each of the above prior art sense amplifier circuits, the delay time which elapses between the instant at which memory cell selection by the word line signal begins and the point at which the corresponding bit line pair differential voltage increases to a predetermined minimum value, will basically depend upon the level of current which can be supplied to charge or discharge the bit line capacitance. In the case of a very large-capacity semiconductor memory, e.g. a 4 MB or 8 MB dymanic RAM memory for example, each bit line has a substantial amount of capacitance. The maximum level of current that can be supplied by a MOS FET when operating in the saturated state can be increased either by reducing the threshold voltage Vt of the FET, or increasing the supply voltage applied to the source electrode. However for reasons such as minimizing the level of standby current of the sense amplifier, it is not practical to lower the threshold voltage of the transistors used in the sense amplifier. As a result, with a prior art sense amplifier which utilizes a reduced level of supply voltage in order to increase the semiconductor memory reliability as described above, it has not been possible to achieve satisfactory speed of sense amplifier operation, i.e. the above-mentioned delay time is excessively long.
The current I.sub.bit that can be supplied to charge or discharge the capacitance of a bit line via a saturated MOS FET is given as follows: ##EQU1##
In the above equation, W denotes the length of the gate electrode of a transistor of the sense amplifier, L denotes the length of the gate electrode, denotes the mobility within a transistor, C.sub.ox denotes the capacitance of the gate oxide layer of a transistor, V.sub.bit denotes the potential of a bit line which is coupled to the gate of that transistor, and Vs denotes the potential of the common node.
It can thus be understood that it has not been possible in the prior art (in the case of a large-capacity semiconductor memory in which a sense amplifier is operated at a level of supply voltage which will ensure high reliability of memory cells) to achieve a sufficient reduction in the delay time which is required for an output voltage from a memory cell, appearing on a bit line, to be amplified as a bit line differential voltage to a predetermined minimum level. It has therefore been difficult to achieve a sufficiently high speed of memory operation.